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[VHDL-FPGA-Verilog] Control_Display

Description: Controlador de display siete segmentos en verilog El archivo contiene selector decodificador multiplexor y archivo para simulacion Sevent segment dispay controler in verilog for basys nexys2 nexys3 fpga boards This file have a decoder, selector multiplexor and a test bench for simulation-Controlador de display siete segmentos en verilog El archivo contiene selector decodificador multiplexor y archivo para simulacion Sevent segment dispay controler in verilog for basys nexys2 nexys3 fpga boards This file have a decoder, selector multiplexor and a test bench for simulation
Platform: | Size: 3072 | Author: megasdra | Hits:

[VHDL-FPGA-Verilog] state_machine

Description: verilog编程状态机实战训练：1.本实例通过实现一个状态机来控制8个LED循环闪亮； 2. 工程在project文件夹里面； 3. 源文件和管脚分配在rtl文件夹里面； 4. 下载文件在download文件夹里面。-verilog programming state machine combat training: 1. This example by implementing a state machine to control 8 LED flashing cycle 2 works in the project folder inside 3 pin assignments in the source file and folder inside rtl 4. download files in download folder inside.
Platform: | Size: 828416 | Author: 李海军 | Hits:

[Voice Compress] bluetooth_Audio_Codec

Description: 蓝牙语音的编解码有三种模式：CVSD、A Law、 u Law。本文件实现以上三种编解码方式。其中包括C代码，matlab代码以及verilog代码。-Bluetooth voice codec has three modes: CVSD, A Law, u Law. This file implements the above three codec. Including the C code, matlab code and verilog code
Platform: | Size: 2102272 | Author: wanghuahua | Hits:

[Communication-Mobile] Volume-1Number-2PP-302-313

Description: here is a copy of pdf file related to verilog -here is a copy of pdf file related to verilog ...
Platform: | Size: 565248 | Author: mohsin | Hits:

[Other] div

Description: 这是我用verilog写的一个电平触发的一个除法器，文件在压缩包内，开发环境是Quartus II。-this is a file of divide using verilog language.
Platform: | Size: 1024 | Author: 张浩 | Hits:

[VHDL-FPGA-Verilog] Binary_to_BCD_Converter

Description: This is a binary to BCD convert designed by using the “shift and add-3 algorithm”. The verilog code of basic cell add-3 is also included in this file.
Platform: | Size: 9216 | Author: WPI | Hits:

[VHDL-FPGA-Verilog] vga_pic

Description: 利用verilog编写的程序，并且实例化了一个rom，将mif文件初始化在rom中，可以实现在vga上显示图片。文字信息等，十分实用。-Use programs written in verilog, and instantiates a rom, rom the mif file initialization, you can achieve the vga display picture. Text information, very useful.
Platform: | Size: 1267712 | Author: 灵湖仙梦 | Hits:

[VHDL-FPGA-Verilog] t4_fifo

Description: FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test script file, we want to be useful.
Platform: | Size: 234496 | Author: 宋国志 | Hits:

[Other] LEDhuadong

Description: LEDhuadong，是基于quarterii写的Verilog程序，可以下载到板子上，是一个工程文件-LEDhuadong, is based quarterii write Verilog program that can be downloaded to the board, is a project file
Platform: | Size: 41984 | Author: 可难 | Hits:

[Other] fifo_verilog

Description: 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
Platform: | Size: 33792 | Author: chenhaoc | Hits:

[VHDL-FPGA-Verilog] myczt

Description: 用Verilog HDL语言对chirp Z变化进行实现，并附带测试文件。-Using Verilog HDL realize changes for chirp Z, and come with a test file.
Platform: | Size: 3072 | Author: 郑羽深 | Hits:

[VHDL-FPGA-Verilog] huffman

Description: 用verilog硬件语言实现了动态huffman编码，能够压缩字符串文件，展示了硬件的压缩率-Using verilog hardware description language to achieve a dynamic huffman coding to compress the string file, showing the hardware compression rate
Platform: | Size: 3072 | Author: 张龙 | Hits:

[VHDL-FPGA-Verilog] Elham-Zahraei-Salehi_-Sina-Saharkhiz-(1)

Description: here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily
Platform: | Size: 150528 | Author: eli | Hits:

[Compress-Decompress algrithms] CAVLE-h264

Description: 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块（Verilog和VHDL两个版本），包含有仿真的testbench测试文件，综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used directly to comprehensive post
Platform: | Size: 604160 | Author: zhanglong | Hits:

[Other] pud_ben

Description: Verilog HDL source code of generating a ROM file (in Quartuss) and testbench in Modelsim (verification)
Platform: | Size: 5120 | Author: Ben | Hits:

[VHDL-FPGA-Verilog] MCU2FPGA_SPI_TB

Description: 本程序使用Verilog语言实现了SPI接口的设计，可以直接烧到FPGA实现与MCU的通信,自带有测试文件。-The program uses the Verilog language design SPI interface, you can burn directly communicate with the FPGA, MCU, comes with a test file.
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] nios_ruanhe_spi_3

Description: 这是我自己写的一个摄像头数据存储SD卡程序，quartus的verilog编写，摄像头采用自己添加的外设接口，数据采用dma采集，SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测，有兴趣的可以测测，初学者可以参考学习，写的代码有点乱，如果有不懂的可以和联系。-This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact
Platform: | Size: 29037568 | Author: 高政 | Hits:

[VHDL-FPGA-Verilog] 02_nonblocking_assignment

Description: verilog HDL file 非阻塞赋值描述 带仿真 用于理解 阻塞赋值与非阻塞赋值的区别-this is a verilog HDL file for non blocking assignment.
Platform: | Size: 2952192 | Author: 刘年 | Hits:

[VHDL-FPGA-Verilog] fpu_double

Description: The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard for double precision floating point arithmetic.
Platform: | Size: 244736 | Author: 丁一 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一份精简指令cpu源代码，用verilog编写，已经通过仿真验证，可以模块化移植。-This is a file of cpu code. The cpu is risc cpu. It is simulated and verificated.And the cpu can be transplanted as a module.
Platform: | Size: 7168 | Author: 耿瑞 | Hits:
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